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Correctness 2017: First International Workshop on Software Correctness for HPC Applications

November 12, 2017

Denver, Colorado, USA

Held in conjunction with SC17: The International Conference for High Performance Computing, Networking, Storage and Analysis
In cooperation with
SIGHPC

Ensuring correctness in high-performance computing (HPC) applications is one of the fundamental challenges that the HPC community faces today. While significant advances in verification, testing, and debugging have been made to isolate software errors (or defects) in the context of non-HPC software, several factors make achieving correctness in HPC applications and systems much more challenging than in general systems software—growing heterogeneity (architectures with CPUs, GPUs, and special purpose accelerators), massive scale computations (very high degree of concurrency), use of combined parallel programing models (e.g., MPI+X), new scalable numerical algorithms (e.g., to leverage reduced precision in floating-point arithmetic), and aggressive compiler optimizations/transformations are some of the challenges that make correctness harder in HPC. The following report lays out the key challenges and research areas of HPC correctness: https://arxiv.org/abs/1705.07478.

As the complexity of future architectures, algorithms, and applications in HPC increases, the ability to fully exploit exascale systems will be limited without correctness. With the continuous use of HPC software to advance scientific and technological capabilities, novel techniques and practical tools for software correctness in HPC are invaluable.

The goal of the Correctness Workshop is to bring together researchers and developers to present and discuss novel ideas to address the problem of correctness in HPC. The workshop will feature contributed papers and invited talks in this area.


Workshop Topics

Topics of interest include, but are not limited to:


Submissions and Format

Authors are invited to submit manuscripts in English structured as technical or experience papers not exceeding 6 pages of content. The 6-page limit includes figures, tables and appendices, but does not include references, for which there is no page limit. Submissions must use the ACM format (please use the sigconf format with default options).

Submitted papers must represent original unpublished research that is not currently under review for any other venue. Papers not following these guidelines will be rejected without review. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information. Papers should be submitted electronically in EasyChair at: https://easychair.org/conferences/?conf=correctness2017.


Proceedings

The proceedings will be archived in both the ACM Digital Library and IEEE Xplore through SIGHPC.


Important Dates


Organizers

Ignacio Laguna, LLNL
Cindy Rubio-González, UC Davis


Program Committee

David Abramson, The University of Queensland, Australia
Eva Darulova, MPI-SWS, Germany
Alastair Donaldson, Imperial College London, UK
Ganesh Gopalakrishnan, University of Utah, USA
Paul Hovland, ANL, USA
Costin Iancu, LBNL, USA
Sriram Krishnamoorthy, PNNL, USA
David Lecomber, Allinea/ARM, UK
Richard Lethin, Reservoir Labs, Yale University, USA
Matthias Müller, RWTH Aachen University, Germany
Feng Qin, The Ohio State University, USA
Nathalie Revol, INRIA - ENS de Lyon, France
Koushik Sen, UC Berkeley, USA
Stephen Siegel, University of Delaware, USA
Armando Solar-Lezama, MIT, USA


Contact Information

Please address workshop questions to Ignacio Laguna (ilaguna@llnl.gov) and/or Cindy Rubio-González (crubio@ucdavis.edu).